1. Field of the Invention
The present invention relates to an electronic assembly that contains filled via holes.
2. Description of Related Art
Integrated circuits are typically enclosed by a package that is soldered to a printed circuit board. The packages may include a substrate that supports the integrated circuit, and plurality of external contacts which couple the substrate to the printed circuit board. The contacts may be solder balls that are attached to the substrate and subsequently reflowed to attach the package to the circuit board.
The substrate typically contains internal routing and conductive vias which provide an electrical path between substrate layers and electrically couple the integrated circuit to the external contacts. Vias are constructed by initially forming holes in the substrate and then plating the inner surface of the holes with a conductive metal material. The plated material provides a conductive path through the substrate. The plating process does not fill, nor is intended to fill, the holes within the substrate. Consequently, each via has a hole extending therethrough.
Highly functional integrated circuits such as microprocessors require packages that have a large number an internal routing traces. The internal routing traces may be formed in multiple layers of the substrate. The multiple layers are coupled together by vias.
Any change in temperature will induce a thermal expansion or contraction of the package, integrated circuit and printed circuit board. The thermal expansion/contraction creates stresses in the vias. It has been found that plated through vias which extend through the length of a multi-layer package will fail when thermally cycled. It would therefore be desirable to provide a more robust via than what is found in the prior art.